AS4LC2M8S0 Datasheet (Alliance Semiconductor) - (AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM

AS4LC2M8S0, (AS4LCxMxxSx) 3.3V 2M X 8/1M X 16 CMOS synchronous DRAM

Output disable/write mask AS4LC2M8S1 and AS4LC2M8S0 AS4LC1M16S0 and AS4LC1M16S1 DataSheet4U.com VSSQ DQ9 DQ8 VCCQ NC UDQM CLK CKE NC A9 A8 A7 A6 A5 A4 VSS RA0 * 10 DataShee Address inputs CA0 * 7 (×16) CA0 * 8 (×8) Bank address (BA) Input/output Row address strobe Column

AS4LC2M8S0 Features

* Organization - 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address AS4LC2M8S1 AS4LC2M8S0 AS4LC1M16S1 AS4LC1M16S0

* All signals referenced to positive edge of clock, fully synchronous