AS4LC4M4F1 - 4M x 4 CMOS DRAM

Alliance Semiconductor

AS4LC4M4F1 Datasheet Preview — Preview of AS4LC4M4F1 PDF

Datasheet Details

Part number	AS4LC4M4F1
Manufacturer	Alliance Semiconductor
File Size	295.20 KB
Description	4M x 4 CMOS DRAM
Datasheet	AS4LC4M4F1_AllianceSemiconductor.pdf

AS4LC4M4F1 Product details

Description

Address inputs Row address strobe Column address strobe Write enable Input/output Output enable Power Ground AS4LC4M4F1 TSOP availability to be determined Selection guide Symbol Maximum RAS access time Maximum column address access time Maximum CAS access time Maximum output enable (OE) access time Minimum read or write cycle time Minimum fast page mode cycle time Maximum operating current Maximum CMOS standby current tRAC tCAA tCAC tOEA tRC tPC ICC1 ICC5 AS4LC4M4F1-50 50 25 12 13 80 25

Features

Organization: 4,194,304 words × 4 bits.
High speed - 50/60 ns RAS access time - 25/30 ns column address access time - 12/15 ns CAS access time.
Refresh - 2048 refresh cycles, 32 ms refresh interval - RAS-only or CAS-before-RAS refresh or self-refresh.
TTL-compatible, three-state I/O.
JEDEC standard package - 300 mil, 24/26-pin SOJ.
Low power consumption - Active: 500 mW max - Standby: 3.6 mW max, CMOS I/O.
Fast page mode.

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Published: Jan 3, 2007 |