Description
www.DataSheet4U.com May 2001 Preliminary ® 3.3V 2M × 8/1M × 16 CMOS synchronous DRAM .
Output disable/write mask
AS4LC2M8S1 and AS4LC2M8S0
AS4LC1M16S0 and AS4LC1M16S1
DataSheet4U.
Features
* Organization
- 1,048,576 words × 8 bits × 2 banks (2M × 8) 11 row, 9 column address - 524,288 words × 16 bits × 2 banks (1M × 16) 11 row, 8 column address
AS4LC2M8S1 AS4LC2M8S0 AS4LC1M16S1 AS4LC1M16S0
* All signals referenced to positive edge of clock, fully synchronous
Applications
* SDRAM commands and functions are decoded from control inputs. Basic commands are as follows:
* Mode register set
* Select column; write
* Auto precharge with read/write
* Deactivate bank
* Select column; read
* Self-refresh
* Deactivate all
