KM416S1120D Datasheet - ETC

KM416S1120D 512K x 16bit x 2 Banks Synchronous DRAM LVTTL

The KM416S1120D is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock c.

KM416S1120D CMOS SDRAM 1M x 16 SDRAM 512K x 16bit x 2 Banks Synchronous DRAM LVTTL Revision 1.4 June 1999 Samsung Electronics reserves the right to change products or specification without notice. -1- Rev. 1.4 (Jun. 1999) KM416S1120D Revision History Revision 1.4 (June, 10th 1999) CMOS SDRAM AC values of tRCD/tRP/tRAS/tRC are returned to the number of clock cycles. Those can be also converted to ns-unit based values by multiplying the number of clock cycles and clock cycle tim.

KM416S1120D Features

* 3.3V power supply LVTTL compatible with multiplexed address Dual banks operation MRS cycle with address key programs -. CAS Latency ( 2 & 3) -. Burst Length (1, 2, 4, 8 & full page) -. Burst Type (Sequential & Interleave) All inputs are sampled at the positive

KM416S1120D_ETC.pdf