EDJ4204EFBG Datasheet - Elpida Memory

EDJ4204EFBG - 1024M words x 4 bits 4G bits DDR3L SDRAM

COVER PRELIMINARY DATA SHEET 4G bits DDR3L SDRAM EDJ4204EFBG (1024M words × 4 bits) EDJ4208EFBG (512M words × 8 bits) EDJ4216EFBG (256M words × 16 bits) Specifications Density: 4G bits Organization 128M words × 4 bits × 8 banks (EDJ4204EFBG) 64M words × 8 bits × 8 banks (EDJ4208EFBG) 32M words × 16 bits × 8 banks (EDJ4216EFBG) Package 78-ball FBGA (EDJ4204EFBG, EDJ4208EFBG) 96-ball FBGA (EDJ4216EFBG) Lea

EDJ4204EFBG Features

* Double-data-rate architecture: two data transfers per clock cycle

* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture

* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re

EDJ4204EFBG-ElpidaMemory.pdf