EDJ1116DJBG Features
* Double-data-rate architecture: two data transfers per clock cycle
* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture
* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re
Datasheet Details
EDJ1116DJBG, EDJ1108DJBG
Elpida Memory
321.34 KB
1g bits ddr3 sdram.
This datasheet PDF includes multiple part numbers: EDJ1116DJBG, EDJ1108DJBG.
Please refer to the document for exact specifications by model.
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EDJ1116DJBG Distributor
