EDJ2108DEBG Datasheet - Elpida Memory

EDJ2108DEBG - 2G bits DDR3 SDRAM

COVER DATA SHEET 2G bits DDR3 SDRAM EDJ2108DEBG (256M words × 8 bits) EDJ2116DEBG (128M words × 16 bits) Specifications Density: 2G bits Organization 32M words × 8 bits × 8 banks (EDJ2108DEBG) 16M words × 16 bits × 8 banks (EDJ2116DEBG) Package 78-ball FBGA (EDJ2108DEBG) 96-ball FBGA (EDJ2116DEBG) Lead-free (RoHS compliant) and Halogen-free Power supply: VDD, VDDQ = 1.5V ± 0.075V Data rate <

EDJ2108DEBG Features

* Double-data-rate architecture: two data transfers per clock cycle

* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture

* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re

EDJ2108DEBG-ElpidaMemory.pdf