EDJ1108DJBG Datasheet - Elpida Memory

EDJ1108DJBG - 1G bits DDR3 SDRAM

COVER DATA SHEET 1G bits DDR3 SDRAM EDJ1108DJBG (128M words × 8 bits) EDJ1116DJBG (64M words × 16 bits) Specifications Density: 1G bits Organization 16M words × 8 bits × 8 banks (EDJ1108DJBG) 8M words × 16 bits × 8 banks (EDJ1116DJBG) Package 78-ball FBGA (EDJ1108DJBG) 96-ball FBGA (EDJ1116DJBG) Lead-free (RoHS compliant) and Halogen-free Power supply: VDD = 1.5V ± 0.075V Data rate 213.

EDJ1108DJBG Features

* Double-data-rate architecture: two data transfers per clock cycle

* The high-speed data transfer is realized by the 8 bits prefetch pipelined architecture

* Bi-directional differential data strobe (DQS and /DQS) is transmitted/received with data for capturing data at the re

EDJ1108DJBG-ElpidaMemory.pdf