GTLP36T612 Datasheet (Fairchild Semiconductor) - 36-Bit LVTTL/GTLP Universal Bus Transceiver

GTLP36T612, 36-Bit LVTTL/GTLP Universal Bus Transceiver

The GTLP36T612 is an 36-bit universal bus transceiver which provides LVTTL to GTLP signal level translation.

It allows for transparent, latched and clocked modes of data transfer.

The device provides a high speed interface for cards operating at LVTTL logic levels and a backplane operating at GTLP l

GTLP36T612 Features

* s Bidirectional interface between GTLP and LVTTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s Partitioned as two 18-Bit transceivers with individual latch timing and output control s VREF pin provides external supply reference voltage for receive