* s Bidirectional interface between GTLP and LVTTL logic levels s Designed with edge rate control circuitry to reduce output noise on the GTLP port s Partitioned as two 18-Bit transceivers with individual latch timing and output control s VREF pin provides external supply reference voltage for receive
GTLP36T612 Datasheet (78.90 KB)
GTLP36T612
Fairchild Semiconductor
78.90 KB
36-bit lvttl/gtlp universal bus transceiver.
GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver
September 2001 Revised July 2002
GTLP36T612 36-Bit LVTTL/GTLP Universal Bus Transceiver
Gener.
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