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HD151011 - Dual BCD Programmable Counter with Synchronous Preset Enable

Datasheet Summary

Description

Down count at the rise edge of clock (CLK), Down count at the fall edge of clock ( CLK ) Jn data is preset at the rise of clock (CLK), the fall of clock (CLK ) Clock inputs (CLK, CLK ) is CMOS level Clock inputs (CLK, CLK ) is TTL level Initialize of Q = "L" Initialize of Q = "H" H: High level L: L

Features

  • High speed operation tpd (CLK or CLK to Q) = 35 ns (typ).
  • High output current Fanout of 10 LS TTL Loads.
  • Wide operating voltage Vcc = 2 to 6 V.
  • Low supply current (Ta = 25°C) Icc (Static) = 4 µA (max) HD151011 Function Table Control Inputs CLR H X.
  • L H PR H X.
  • H L SPE H L.
  • C/T X X H L.
  • Mode Generally count Synchronous preset.
  • Initialize of Q out.

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Datasheet Details

Part number HD151011
Manufacturer Hitachi Semiconductor
File Size 75.66 KB
Description Dual BCD Programmable Counter with Synchronous Preset Enable
Datasheet download datasheet HD151011 Datasheet
Additional preview pages of the HD151011 datasheet.

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Full PDF Text Transcription

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HD151011 Dual BCD Programmable Counter with Synchronous Preset Enable ADE-205-100(Z) Rev 0 April 1995 The HD151011 has BCD decimal two digits down counter and D-type Flip Flop. The counter can set up to max 99 counts and synchronous preset ( SPE) input can preset the data. When the count value is 0, the next clock pulse presets the data to invert the output. D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge. It is applied to generate AC signal for STN type liquid crystal and general-use divider.
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