HD151011 - Dual BCD Programmable Counter with Synchronous Preset Enable
Down count at the rise edge of clock (CLK), Down count at the fall edge of clock ( CLK ) Jn data is preset at the rise of clock (CLK), the fall of clock (CLK ) Clock inputs (CLK, CLK ) is CMOS level Clock inputs (CLK, CLK ) is TTL level Initialize of Q = "L" Initialize of Q = "H" H: High level L: L
HD151011 Dual BCD Programmable Counter with Synchronous Preset Enable ADE-205-100(Z) Rev 0 April 1995 The HD151011 has BCD decimal two digits down counter and D-type Flip Flop.
The counter can set up to max 99 counts and synchronous preset ( SPE) input can preset the data.
When the count value is 0, the next clock pulse presets the data to invert the output.
D-type Flip Flop takes the counter output as clock pulse, whose data is transferred to output at the rise edge.
It is applied to generate
HD151011 Features
* High speed operation tpd (CLK or CLK to Q) = 35 ns (typ)
* High output current Fanout of 10 LS TTL Loads
* Wide operating voltage Vcc = 2 to 6 V
* Low supply current (Ta = 25°C) Icc (Static) = 4 µA (max) HD151011 Function Table Control Inputs CLR H X
