H55S1262EFP-60E Datasheet - Hynix Semiconductor

H55S1262EFP-60E, 128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O

www.DataSheet4U.com 128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O Specification of 128M (8Mx16bit) Mobile SDRAM Memory Cell Array - Organiz.
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Datasheet Details

Part number:

H55S1262EFP-60E

Manufacturer:

Hynix Semiconductor

File Size:

796.95 KB

Description:

128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O

Features

* Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK) MULTIBANK OPERATION - Internal 4bank operation - During burst Read or Write operation, burst Read or Write for a different bank is performed. - During b

Applications

* which requires large memory density and high bandwidth. It is organized as 4banks of 2,097,152x16. Mobile SDRAM is a type of DRAM which operates in synchronization with input clock. The Hynix Mobile SDRAM latch each control signal at the rising edge of a basic input clock (CLK) and input/output data

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H55S1262EFP-60E 128MBit MOBILE SDR SDRAMs based 4Bank x16 Hynix Semiconductor

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