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H55S1262EFP-60M - 128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O

This page provides the datasheet information for the H55S1262EFP-60M, a member of the H55S1262EFP-60E 128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O family.

Datasheet Summary

Description

and is subject to change without notice.

Hynix does not assume any responsibility for use of circuits described.

No patent licenses are implied.

Features

  • Standard SDRAM Protocol Clock Synchronization Operation - All the commands registered on positive edge of basic input clock (CLK).

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Datasheet Details

Part number H55S1262EFP-60M
Manufacturer Hynix Semiconductor
File Size 796.95 KB
Description 128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O
Datasheet download datasheet H55S1262EFP-60M Datasheet
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www.DataSheet4U.com 128MBit MOBILE SDR SDRAMs based on 2M x 4Bank x16 I/O Specification of 128M (8Mx16bit) Mobile SDRAM Memory Cell Array - Organized as 4banks of 2,097,152 x16 This document is a general product description and is subject to change without notice. Hynix does not assume any responsibility for use of circuits described. No patent licenses are implied. Rev 1.2 /Aug. 2009 1 11 128Mbit (8Mx16bit) Mobile SDR Memory H55S1262EFP Series www.DataSheet4U.com Document Title 4Bank x 2M x 16bits Synchronous DRAM Revision History Revision No. 0.1 0.2 Initial Draft - Define IDD specification -. Correct Temp range(p.9 & p.10) -. Modify IDD Values(p.11 & p.12) -. Omit a typo in a package inforamtion -. Modify package information(add tolerance) History Draft Date Sep. 2007 Feb.
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