HY5DU28422AT - 3rd 128M DDR SDRAM
and is subject to change without notice.
Hynix semiconductor does not assume any responsibility for use of circuits described.
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Rev.
0.4/May.
02 1 www.DataSheet4U.com HY5DU28422A(L)T HY5DU28822A(L)T HY5DU281622A(L)T Revision History 1.
Revision 0.2 (Nov.01) 1) Devic
HY5DU28422AT Features
* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data strobe
