* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da
HY5DU28422T Datasheet (1.54 MB)
HY5DU28422T
Hynix Semiconductor
1.54 MB
2nd 128m ddr sdram.
HY5DU28422T HY5DU28822T HY5DU281622T
2nd 128M DDR SDRAM
HY5DU28422T HY5DU28822T HY5DU281622T
Revision 1.3 April 2001
Rev. 1.3 / Apr. 2001
This doc.
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