HY5DU561622AT - (HY5DU56xx22A(L)T) 256M-S DDR SDRAM
and is subject to change without notice.
Hynix semiconductor does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
0.4/ May.
02 DataSheet4U.com www.DataSheet4U.com HY5DU56422A(L)T HY5DU56822A(L)T HY5DU561622A(L)T Revision History 1.
Revision 0.2 (
HY5DU561622AT Features
* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da
