* VDD/VDDQ = 2.5 ~ 2.7V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional data s
HY5DU561622CT Datasheet (267.11 KB)
HY5DU561622CT
Hynix Semiconductor
267.11 KB
(hy5du56xx22ct) 256m-p ddr sdram.
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HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU561622CT-D4/D43
256M-P DDR SDRAM
HY5DU56422CT-D4/D43 HY5DU56822CT-D4/D43 HY5DU56162.
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