HY5DU561622DTP - (HY5DU56x22DTP) 256M DDR SDRAM
and is subject to change without notice.
Hynix semiconductor does not assume any responsibility for use of circuits described.
No patent licenses are implied.
Rev.
0.1 /May 2004 www.DataSheet4U.com HY5DU56422D(L)TP HY5DU56822D(L)TP HY5DU561622D(L)TP DESCRIPTION PRELIMINARY The Hynix HY5DU56422D(L
HY5DU561622DTP Features
* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da
