* VDD, VDDQ = 2.5V +/- 0.2V All inputs and outputs are compatible with SSTL_2 interface Fully differential clock inputs (CK, /CK) operation Double data rate interface Source synchronous - data transaction aligned to bidirectional da
HY5DU561622T Datasheet (370.15 KB)
HY5DU561622T
Hynix Semiconductor
370.15 KB
(hy5du56xxx(l)t) 2nd 256m ddr sdram.
m o .c U 4 t e e h S a at .D w w w
HY5DU56422(L)T HY5DU56822(L)T HY5DU561622(L)T
m 2nd 256M DDR SDRAM o .c U 4 t e e h S a t a .D w w w
HY5DU56422(L.
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