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ICS889872 - DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION

ICS889872 Description

www.DataSheet4U.com PRELIMINARY DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION ICS889872 .
The ICS889872 is a high speed Differential-toLVDS Buffer/Divider w/Internal Termination and is a HiPerClockS™ member of the HiPerClockS™family of high.

ICS889872 Features

* Three LVDS outputs Frequency divide select options: ÷4, ÷6: >2GHz, ÷8, ÷16: >1.6GHz IN, nIN input can accept the following differential input levels: LVPECL, LVDS, CML Output frequ

ICS889872 Applications

* Equal to VDD
* 1.4V (approx. ). Maximum sink/source current is 0.5mA. Termination input. Leave pin floating. Non-inverting LVPECL differential clock input. RT = 50Ω termination to VT. Power supply ground. Pullup Select pins. Logic HIGH if left unconnected (÷16 mode). S0 = LSB. Input threshol

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Datasheet Details

Part number
ICS889872
Manufacturer
IDT
File Size
1.09 MB
Datasheet
ICS889872_IDT.pdf
Description
DIFFERENTIAL-TO-LVDS BUFFER/DIVIDER W/INTERNAL TERMINATION

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DIFFERENTIAL-TO-LVDS BUFFER DIVIDER INTERNAL TERMINATION IDT
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