IDT74SSTU32865 Datasheet - IDT

IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER

APPLICATIONS: * Along with CSPU877/A/D DDR2 PLL, provides complete solution for DDR2 DIMMs * Optimized for DDR2-400/533 (PC2-3200/4300) JEDEC Raw Card D The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V VDD operation. All clock and data inputs.

IDT74SSTU32865 Features

* 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Control inputs compatible with LVCMOS levels Flow-through architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-88

IDT74SSTU32865_IDT.pdf