IDT74SSTU32865 - 28-BIT 1:2 REGISTERED BUFFER

IDT

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Datasheet Details

Part number	IDT74SSTU32865
Manufacturer	IDT
File Size	244.14 KB
Description	28-BIT 1:2 REGISTERED BUFFER
Datasheet	IDT74SSTU32865_IDT.pdf

IDT74SSTU32865 Product details

Description

APPLICATIONS: Along with CSPU877/A/D DDR2 PLL, provides complete solution for DDR2 DIMMs Optimized for DDR2-400/533 (PC2-3200/4300) JEDEC Raw Card D The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed for 1.7V to 1.9V VDD operation.All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS.All outputs are 1.8V CMOS drivers that have been optimized to drive the DDR2 DIMM load.The SSTU32865 operates from

Features

1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Control inputs compatible with LVCMOS levels Flow-through architecture for optimum PCB design Latch-up performance exceeds 100mA ESD >2000V per MIL-STD-883, Method 3015; >200V using machine model (C = 200pF, R = 0).
Available in 160-pin CTBGA package.

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Published: Oct 3, 2007 |