IDT74SSTUAE32866A Datasheet - IDT

IDT74SSTUAE32866A 25-BIT CONFIGURABLE REGISTERED BUFFER

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.425V to 1.575V VDD operation. The control inputs are LVCMOS. All outputs are 1.5-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. IDT74SSTUAE32866A operates from a differential clock (CLK and CLK). D.

www.DataSheet4U.com DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 IDT74SSTUAE32866A outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS and CSR inputs and will gate the Qn outputs from changing states when both DCS and CSR inputs are high. If either DCS and CSR input is low, the Qn outputs will function normally. The RESET input has priority over the DCS and CSR control and will force the outputs low. If the DCS-control functionality is no.

IDT74SSTUAE32866A Features

* Supports 1.5V VDD operation for DDR2 DIMMs

* 25-bit 1:1 or 14-bit 1:2 registered buffer with parity check

* functionality Supports LVCMOS switching levels on C0, C1, and RESET inputs Low voltage operation: VDD = 1.425V to 1.575V Available in 96-ball LFBG

IDT74SSTUAE32866A Datasheet (666.82 KB)