IS46DR16640C - DDR2 DRAM
MAY 2013 ISSI's 1Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation.
The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.
ADDRESS TABLE Parameter Co
IS46DR16640C Features
* Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
* JEDEC standard 1.8V I/O (SSTL_18-compatible)
* Double data rate interface: two data transfers per clock cycle
* Differential data strobe (DQS, DQS)
* 4-bit prefetch architecture
* On chip DLL to align DQ an
