* 100 percent bus utilization
* No wait cycles between Read and Write
* Internal self-timed write cycle
* Individual Byte Write Control
* Single R/W (Read/Write) control pin
* Clock controlled, registered address, data and control
* Interleaved
IS61NVP51218B Datasheet (940.52 KB)
IS61NVP51218B
ISSI
940.52 KB
9mb state bus sram.
IS61NLP25636B/IS61NVP/NVVP25636B IS61NLP51218B/IS61NVP/NVVP51218B ® Long-term Support World Class Quality 256K x 36 and 512K x 18 9Mb, PIPELINE 'NO.
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