* 100 percent bus utilization
* No wait cycles between Read and Write
* Internal self-timed write cycle
* Individual Byte Write Control
* Single R/W (Read/Write) control pin
* Clock controlled, registered address, data and control
* Interleaved
IS61NVP51236B Datasheet (1.92 MB)
IS61NVP51236B
ISSI
1.92 MB
18mb state bus synchronous sram.
IS61NLP51236(32)B/IS61NVP51236(32)B/IS61NVVP51236(32)B IS61NLP102418B/IS61NVP102418B/IS61NVVP102418B
512K x36 and 1024K x18 18Mb, PIPELINE 'NO WAIT' .
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