IC42S32200 Datasheet - Integrated Circuit Systems

IC42S32200 512K Words x 32 Bits x 4 Banks (64-MBIT) SYNCHRONOUS DYNAMIC RAM

The ICSI IC42S32200 and IC42S32200L is a high-speed CMOS configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits.Read and write acce.

IC42S32200 IC42S32200L Document Title 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM Revision History www.datasheet4u.com Revision No History Initial Draft Obselete partial refresh function Obselete 5ns speed grade Change ICC3P from 3mA to 5mA Revise typo Revise p.20,p.22 data and p.28 typo Draft Date September 26,2002 September 05,2003 April 27,2004 February 04,2005 Remark 0A 0B 0C 0D The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the s.

IC42S32200 Features

* Concurrent auto www.datasheet4u.com precharge

* Clock rate:166/143/125 MHz

* Fully synchronous operation

* Internal pipelined architecture

* Four internal banks (512K x 32bit x 4bank)

* Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:int

IC42S32200 Datasheet (0.96 MB)