IC42S32202L Description
IC42S32202/L Document Title 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM Revision History www.datasheet4u.com Revision No History Initial Draft Draft D.
The ICSI IC42S32202 and IC42S32202L is a high-speed CMOS configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered.
IC42S32202L Features
* Concurrent auto www. datasheet4u. com precharge
* Clock rate:166/143/125 MHz
* Fully synchronous operation
* Internal pipelined architecture
* Four internal banks (512K x 32bit x 4bank)
* Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:int
IC42S32202L Applications
* requiring high memory bandwidth. ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2000, Integrated Circuit
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