IC42S32202 Datasheet - Integrated Circuit Solution

IC42S32202 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM

The ICSI IC42S32202 and IC42S32202L is a high-speed CMOS configured as a quad 512K x 32 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal,CLK). Each of the 512K x 32 bit banks is organized as 2048 rows by 256 columns by 32 bits.Read and write acce.

IC42S32202/L Document Title 512K x 32 Bit x 4 Banks (64-MBIT) SDRAM Revision History www.datasheet4u.com Revision No History Initial Draft Draft Date August 17,2004 Remark 0A The attached datasheets are provided by ICSI. Integrated Circuit Solution Inc reserve the right to change the specifications and products. ICSI will answer to your questions about device. If you have any questions, please contact the ICSI offices. Integrated Circuit Solution Inc. DR042-0C 08/17/2004 1 IC42S32202/L.

IC42S32202 Features

* Concurrent auto www.datasheet4u.com precharge

* Clock rate:166/143/125 MHz

* Fully synchronous operation

* Internal pipelined architecture

* Four internal banks (512K x 32bit x 4bank)

* Programmable Mode -CAS#Latency:2 or 3 -Burst Length:1,2,4,8,or full page -Burst Type:int

IC42S32202_IntegratedCircuitSolution.pdf