ICS2509C - 3.3V Phase-Lock Loop Clock Driver
The ICS2509C is a high performance, low skew, low jitter clock driver.
It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal.
It is specifically designed for use with synchronous SDRAMs.
The ICS2509C operates at 3.3V VCC and drives
ICS2509C Features
* Meets or exceeds PC133 registered DIMM specification 1.1 Spread Spectrum Clock Compatible Distributes one clock input to one bank of five and one bank of four outputs Separate output enable(OEA,OEB) for each ou
