* rmance is affected by the parasitic circuit elements. If the parasitics were not present, the slope of the curves would maintain a value of unity regardless of the switching speed. The circuit used to obtain the data is constructed to minimize common inductance in the drain and gate circuit loops an
MTB20N20E Datasheet (258.71 KB)
MTB20N20E
Motorola
258.71 KB
Tmos power fet.
MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MTB20N20E/D ™ Data Sheet TMOS E-FET.™ High Energy Power FET D2PAK for Surface Mount De.
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