CS5825 - 28:4 LVDS Receiver
CS5825 receives four LVDS data channels and one LVDS clock channel.
Each data channel is deserialized into 7-bit parallel data bus for output.
The clock channel is used for frame sync and fed into an internal PLL that generates the 7X serial clock used in the deserializer.
A digital phase alignment
CS5825 Features
* CS5825 28:4 LVDS Receiver
* Four 7-bit serial data LVDS channels and one clock LVDS channel.
* Compatible with ANSI TIA/EIA-644 LVDS standard.
* Wide serial clocking speed ranges from 31MHz to 68MHz.
* Support open-safe LVDS design.
* Fully integrated on-chi
