74AUP1G373 Datasheet, latch, NXP Semiconductors

74AUP1G373 Features

  • Latch s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95

PDF File Details

Part number:

74AUP1G373

Manufacturer:

NXP ↗ Semiconductors

File Size:

144.41kb

Download:

📄 Datasheet

Description:

Low-power d-type transparent latch. The 74AUP1G373 provides the single D-type transparent latch with 3-state output. While the latch-enable (LE) input is high, the Q out

Datasheet Preview: 74AUP1G373 📥 Download PDF (144.41kb)
Page 2 of 74AUP1G373 Page 3 of 74AUP1G373

74AUP1G373 Application

  • Applications using IOFF. The IOFF circuitry disables the output, preventing the damaging backflow current through the device when it is powered down.

TAGS

74AUP1G373
Low-power
D-type
transparent
latch
NXP Semiconductors

📁 Related Datasheet

74AUP1G373 - Low-power D-type transparent latch (nexperia)
74AUP1G373 Low-power D-type transparent latch; 3-state Rev. 9 — 20 January 2022 Product data sheet 1. General description The 74AUP1G373 is a sing.

74AUP1G373-Q100 - Low-power D-type transparent latch (nexperia)
74AUP1G373-Q100 Low-power D-type transparent latch; 3-state Rev. 3 — 20 January 2022 Product data sheet 1. General description The 74AUP1G373-Q100.

74AUP1G374 - Low-power D-type flip-flop (nexperia)
74AUP1G374 Low-power D-type flip-flop; positive-edge trigger; 3-state Rev. 10 — 21 January 2022 Product data sheet 1. General description The 74AU.

74AUP1G374-Q100 - Low-power D-type flip-flop (nexperia)
74AUP1G374-Q100 Low-power D-type flip-flop; positive-edge trigger; 3-state Rev. 3 — 21 January 2022 Product data sheet 1. General description The .

74AUP1G32 - Low-power 2-input OR gate (NXP)
.. 74AUP1G32 Low-power 2-input OR gate Rev. 01 — 2 August 2005 Product data sheet 1. General description The 74AUP1G32 is a high-pe.

74AUP1G32 - SINGLE 2 INPUT POSITIVE OR GATE (Diodes)
74AUP1G32 SINGLE 2 INPUT POSITIVE OR GATE Description The Advanced Ultra Low Power (AUP) CMOS logic family is designed for low power and extended bat.

74AUP1G32 - Low-power 2-input OR-gate (nexperia)
74AUP1G32 Low-power 2-input OR-gate Rev. 11 — 17 January 2022 Product data sheet 1. General description The 74AUP1G32 is a single 2-input OR gate. S.

74AUP1G32-Q100 - Low-power 2-input OR-gate (nexperia)
74AUP1G32-Q100 Low-power 2-input OR-gate Rev. 5 — 17 January 2022 Product data sheet 1. General description The 74AUP1G32-Q100 provides the single 2.

74AUP1G3208 - Low Power 3-Input OR-AND Gate (NXP)
.. 74AUP1G3208 Low-power 3-input OR-AND gate Rev. 01 — 29 November 2006 Product data sheet 1. General description The 74AUP1G3208 i.

74AUP1G3208 - Low-power 3-input OR-AND gate (nexperia)
74AUP1G3208 Low-power 3-input OR-AND gate Rev. 10 — 9 May 2023 Product data sheet 1. General description The 74AUP1G3208 is a single 3-input OR-AND .

Since 2006. D4U Semicon.   |   Datasheet4U.com   |   Contact Us   |   Privacy Policy   |   Purchase of parts