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PHT6N03LT TrenchMOS transistor Logic level FET

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Description

Philips Semiconductors Product specification TrenchMOS™ transistor Logic level FET .
GENERAL DESCRIPTION N-channel enhancement mode logic level field-effect power transistor using ’trench’ technology.

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Features

* ’Trench’ technology
* Very low on-state resistance
* Fast switching
* Stable off-state characteristics
* High thermal cycling performance
* Surface mounting package PHT6N03LT SYMBOL d QUICK REFERENCE DATA VDSS = 30 V ID = 5.9 A g s RDS(ON) ≤ 30 m

Applications

* The PHT6N03LT is supplied in the SOT223 surface mounting package. PINNING PIN 1 2 3 tab gate drain source drain 4 1 2 3 LIMITING VALUES Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL PARAMETER VDSS VDGR VGS ID IDM PD Tj, Tstg Drain-source voltage Drain-gate vo

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