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DS90LV110T 1 to 10 LVDS Data/Clock Distributor

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Description

1 to 10 LVDS Data/Clock Distributor July 2001 DS90LV110T 1 to 10 LVDS Data/Clock Distributor General .
DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation.

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Datasheet Specifications

Part number
DS90LV110T
Manufacturer
National Semiconductor
File Size
468.40 KB
Datasheet
DS90LV110T_NationalSemiconductor.pdf
Description
1 to 10 LVDS Data/Clock Distributor

Features

* n Low jitter 800 Mbps fully differential data path n 145 ps (typ) of pk-pk jitter with PRBS = 223
* 1 data pattern at 800 Mbps n Single +3.3 V Supply n Less than 413 mW (typ) total power dissipation n Balanced output impedance n Output channel-to-channel skew is 35ps (typ) n Differential outpu

Applications

* for higher speed links with improved signal quality. It can also be used for clock distribution up to 400MHz. The DS90LV110 accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks. The LVDS outputs can be put into TRI-STATE by use of the enable pin. For more details, ple

DS90LV110T Distributors

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