Description
The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.
Features
- es.
- 3 MHz.
- 40 MHz clock embedded and DC-Balancing 24:1
and 1:24 data transmissions Transmitter and Receiver.
- User selectable clock edge for parallel data on both
coupling interface with no external coding required Individual power-down controls for both Transmitter and Receiver Embedded clock CDR (clock and data recovery) on Receiver and no external source of reference clock needed All codes RDL (random data lock) to support livepluggable.
DS99R101_NationalSemiconductor.pdf