DS99R101 Datasheet (National Semiconductor) - (DS99R101 / DS99R102) 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

DS99R101, (DS99R101 / DS99R102) 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer

The DS99R101/DS99R102 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock information.

This single serial stream simplifies transferring a 24-bit bus over PCB traces and cable by eliminating the skew problems between parallel data and

DS99R101 Features

* 3 MHz

* 40 MHz clock embedded and DC-Balancing 24:1 and 1:24 data transmissions Transmitter and Receiver

* User selectable clock edge for parallel data on both coupling interface with no external coding required Individual power-down controls for both Transmitter and Receiver Embed