Description
DS99R105/DS99R106 3-40MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer October 2007 www.DataSheet4U.com DS99R105/DS99R106 3-40MHz DC-Balance.
The DS99R105/DS99R106 Chipset translates a 24-bit parallel bus into a fully transparent data/control LVDS serial stream with embedded clock informatio.
Features
* pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects.
* Internal DC Balancing encode/decode
* Supports AC
Applications
* LOCK output flag to ensure data integrity at Receiver side Balanced TSETUP/THOLD between RCLK and RDATA on Receiver side PTO (progressive turn-on) LVCMOS outputs to reduce EMI and minimize SSO effects All LVCMOS inputs and control pins have internal pulldown On-chip filters for PLLs on Transmitter a
