P06B03LVG Datasheet (Niko) - Dual P-Channel Logic Level Enhancement Mode Field Effect Transistor

P06B03LVG, Dual P-Channel Logic Level Enhancement Mode Field Effect Transistor

Logic Level Enhancement P06B03LVG NIKO-SEM Dual P-Channel Mode Field Effect Transistor www.DataSheet4U.com SOP-8 Lead Free PRODUCT SUMMARY V(BR)DSS -30 RDS(ON) 50m£[ ID -6A G :GATE D :DRAIN S :SOURCE ABSOLUTE MAXIMUM RATINGS (TC = 25 °C Unless Otherwise Noted) PARAMETERS/TEST CONDITIONS Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Current Power Dissipation 1 SYMBOL VDS VGS LIMITS -30 ±20 -6 -5 UNITS V V TC = 25 °C TC = 70 °C ID IDM A -30 2.5 1.3 W TC