NB3L8543S - 2.5V/3.3V Differential 2:1 MUX to 4 LVDS Clock Fanout Buffer Outputs
NB3L8543S Features
* a multiplexed input which can be driven by either a differential or single
* ended input to allow for the distribution of a lower speed clock along with the high speed system clock. The CLK_SEL pin will select the differential CLK and CLK inputs when LOW (or left open and pulled LOW by the int
