PLL650-08 - Network LAN Clock Source

Name: PLL650-08
SKU: PLL650-08-534473

PhaseLink

Datasheet Details

The PLL 650-08 is a low cost, low jitter, and high performance clock synthesizer.

w w Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. 1 output fixed at 100MHz , 1 output fixed at 125MHz . Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 8-Pin 150mil SOIC. at . D w h S a t e e 4U m o . c.

📁 PLL650-08 Similar Datasheet

PLL0210A - PHASE LOCKED LOOP (Z-Communications)
PLL0930A - PHASE LOCKED LOOP (Z-Communications)
PLL1000A - PHASE LOCKED LOOP (Z-Communications)
PLL102-03 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-04 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-05 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-10 - Low Skew Output Buffer (PhaseLink Corporation)
PLL102-108 - Programmable DDR Zero Delay Clock Driver (PhaseLink Corporation)

Other Datasheets by PhaseLink

Published: Feb 10, 2006 |