ICS9FG1201H Datasheet - Renesas

ICS9FG1201H Frequency Gearing Clock

The ICS9FG1201H follows the Intel DB1200G Rev 1.0 Differential Buffer Specification. This buffer provides 12 output clocks for CPU Host Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs are configured with two groups. Both groups (DIF 9:0) and (DIF 11:10) can be equal to or have a g.

ICS9FG1201H Features

* Benefits

* Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)

* Power up default is all outputs in 1:1 mode

* DIF_(9:0) can be “gear-shifted” from the input CPU Host Clock

* DIF_(11:10) can be “gear-shifted” from the input CPU Host Clock

* Spread spectrum com

ICS9FG1201H-Renesas.pdf