Datasheet4U Logo Datasheet4U.com

MK2049-45

CLOCK PLL

MK2049-45 Features

* Packaged in 20 pin SOIC

* 3.3 V + 5% operation

* Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E

* Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50

MK2049-45 General Description

The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO based and uses a pullable crystal to track signal wander and attenuate input jitter. The second PLL is a translator for frequency multiplication. Basic configura.

MK2049-45 Datasheet (377.46 KB)

Preview of MK2049-45 PDF

Datasheet Details

Part number:

MK2049-45

Manufacturer:

Renesas ↗

File Size:

377.46 KB

Description:

Clock pll.

📁 Related Datasheet

MK2049-45 3.3V Communications Clock PLL (Integrated Circuit Systems)

MK2049-45 CLOCK PLL (Renesas)

MK2049-01 Communications Clock PLL (Integrated Circuit Systems)

MK2049-02 Communications Clock PLLs (Integrated Circuit Systems)

MK2049-03 Communications Clock PLLs (Integrated Circuit Systems)

MK2049-34 3.3 V Communications Clock PLL (Integrated Circuit Systems)

MK2049-34 CLOCK VCXO PLL (Renesas)

MK2049-34A 3.3 Volt Communications Clock VCXO PLL (Integrated Circuit Systems)

MK2049-35 3.3 V Communications Clock PLL (Integrated Circuit Systems)

MK2049-36 3.3 V Communications Clock PLL (Integrated Circuit Systems)

TAGS

MK2049-45 CLOCK PLL Renesas

Image Gallery

MK2049-45 Datasheet Preview Page 2 MK2049-45 Datasheet Preview Page 3

MK2049-45 Distributor