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MK2049-45 CLOCK PLL

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Description

3.3 VOLT COMMUNICATIONS CLOCK PLL DATASHEET MK2049-45 .
The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation.

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Features

* Packaged in 20 pin SOIC
* 3.3 V + 5% operation
* Meets the TR62411, ETS300 011, and GR-1244 specification for MTIE, Pull-in/Hold-in Range, Phase Transients, and Jitter Generation for Stratum 3, 4, and 4E
* Accepts multiple inputs: 8 kHz backplane clock, or 10 to 50

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