K4S280832B - 128M-bit SDRAM

Samsung Electronics

Datasheet Details

The K4S280832B is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 4,194,304 words by 8 bits, fabricated with

JEDEC standard 3.3V power supply.
LVTTL compatible with multiplexed address.
Four banks operation.
MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave).
All inputs are sampled at the positive going edge of the system clock.
Burst read single-bit write operation.
DQM for masking.
Auto & self refresh.
64ms refresh period (4K cycle.

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