K4S281632B-TL10 - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

This page provides the datasheet information for the K4S281632B-TL10, a member of the K4S 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL family.

Datasheet Summary

Description

The K4S281632B is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology.

Features

JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) CMOS SDRAM.

Samsung semiconductor

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Datasheet Details

Part number	K4S281632B-TL10
Manufacturer	Samsung semiconductor
File Size	108.47 KB
Description	128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
Datasheet	K4S281632B-TL10 Datasheet
Additional preview pages of the K4S281632B-TL10 datasheet.

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Other Datasheets by Samsung semiconductor

K4S281632B-TL1H - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-TL1L - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-TL75 - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-TL80 - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-TC10 - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-TC1H - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-TC1L - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL
K4S281632B-TC75 - 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL

Full PDF Text Transcription

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K4S281632B CMOS SDRAM 128Mbit SDRAM 2M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.0 Aug. 1999 * Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.0 Aug. 1999 K4S281632B 2M x 16Bit x 4 Banks Synchronous DRAM FEATURES • • • • JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock.

Published: Apr 7, 2005 |