K4S281633D-RL Datasheet - Samsung semiconductor

K4S281633D-RL 8Mx16 SDRAM 54CSP

The K4S281633D is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every c.

Preliminary K4S281633D-RL(N) CMOS SDRAM 8Mx16 SDRAM 54CSP (V DD/V DDQ 3.0V/3.0V & 3.3V/3.3V) Revision 0.6 November 2001 Rev. 0.6 Nov. 2001 Preliminary K4S281633D-RL(N) Revision History Revision 0.0 (February 21. 2001, Target) CMOS SDRAM First generation of 128Mb Low Power SDRAM without special function (V DD 3.0V, V DDQ 3.0V) Revision 0.1 (June 4. 2001, Target) Addition of DC Current value. Revision 0.2 (June 20. 2001, Target) Changed device name from low.

K4S281633D-RL Features

* 3.0V & 3.3V power supply.

* LVTTL compatible with multiplexed address.

* Four banks operation.

* MRS cycle with address key programs. -. CAS latency (1 & 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).

* All inputs

K4S281633D-RL_Samsungsemiconductor.pdf

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Datasheet Details

Part number:

K4S281633D-RL

Manufacturer:

Samsung semiconductor

File Size:

71.00 KB

Description:

8mx16 sdram 54csp.

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