K4S510832M Datasheet - Samsung semiconductor

K4S510832M 16M x 8bit x 4 Banks Synchronous DRAM LVTTL

The K4S510832M is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 16,777,216 words by 8 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock.

K4S510832M Preliminary CMOS SDRAM 512Mbit SDRAM 16M x 8bit x 4 Banks Synchronous DRAM LVTTL www.DataSheet4U.com Revision 0.2 Dec. 2001 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.2 Dec. 2001 K4S510832M Revision History Revision 0.0 (Mar. 2001) Revision 0.1 (Aug. 2001) Defined target DC characteristics. Preliminary CMOS SDRAM Revision 0.2 (Dec. 2001) Changed "Target" to "Preliminary". Redefined DC characteristics. .

K4S510832M Features

* JEDEC standard 3.3V power supply

* LVTTL compatible with multiplexed address

* Four banks operation

* MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)

* All inputs are

K4S510832M_Samsungsemiconductor.pdf