K4S641632D Datasheet - Samsung semiconductor

K4S641632D 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL

The K4S641632D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock .

K4S641632D CMOS SDRAM 64Mbit SDRAM 1M x 16Bit x 4 Banks Synchronous DRAM LVTTL Revision 0.3 June 2000 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.3 June 2000 K4S641632D Revision History Revision 0.1 (May 2000) Changed tOH of K4S280432C-TC75/TL75 from 2.7ns to 3.0ns. CMOS SDRAM Revision 0.2 (May 2000) Added -70 (7.0ns) Speed. Revision 0.3 (June 2000) Added -60 (6.0ns) and -55(5.5ns) Speed. Rev. 0.3.

K4S641632D Features

* JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled a

K4S641632D Datasheet (115.07 KB)