K4S641632D Datasheet | Samsung Semiconductor

FEATURES - - - - JEDEC standard 3.3V power supply LVTTL patible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (4K cycle) CMOS SDRAM GENERAL DESCRIPTION The K4S641632D is 67,108,864 bits synchronous high data rate Dynamic RAM organized as 4 x 1,048,576 words by 16 bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. - - - - - ORDERING INFORMATION Part No. K4S641632D-TC/L55 K4S641632D-TC/L60 K4S641632D-TC/L70 K4S641632D-TC/L75 K4S641632D-TC/L80 K4S641632D-TC/L1H K4S641632D-TC/L1L Max Freq. 183MHz(CL=3) 166MHz(CL=3) 143MHz(CL=3) 133MHz(CL=3) 125MHz(CL=3) 100MHz(CL=2) 100MHz(CL=3) LVTTL 54 TSOP(II) Interface Package FUNCTIONAL BLOCK DIAGRAM I/O Control Data Input Register LDQM Bank Select 1M x 16 Sense AMP 1M x 16 1M x 16 1M x 16 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address Register CLK ADD Column Decoder Col. Buffer Latency & Burst Length LRAS LCBR LCKE LRAS LCBR LWE LCAS Programming Register LWCBR LDQM Timing Register L(U)DQM - Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.3 June 2000 PIN CONFIGURATION (Top view) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BA0 BA1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53...