K7B321825M Datasheet - Samsung semiconductor

K7B321825M 1Mx36 & 2Mx18 Synchronous SRAM

The K7B323625M and K7B321825M are 37,748,736-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium and Power PC based System. It is organized as 1M(2M) words of 36(18) bits and integrates address and control registers, a 2-bit burst address counter a.

K7B323625M K7B321825M Document Title 1Mx36 & 2Mx18 Synchronous SRAM 1Mx36 & 2Mx18-Bit Synchronous Burst SRAM Revision History Rev. No. 0.0 0.1 0.2 0.3 History 1. Initial draft 1. Add 165FBGA package 1. Update JTAG scan order 1. Change pin out for 165FBGA - x18/x36 ; 11B => from A to NC , 2R ==> from NC to A . 1. Insert pin at JTAG scan order of 165FBGA in connection with pin out change - x18/x36 ; insert Pin ID of 2R to BIT number of 69 1. Add Icc, Isb, Isb1 and Isb2 values. 1. Correct the pi.

K7B321825M Features

* Synchronous Operation.

* On-Chip Address Counter.

* Self-Timed Write Cycle.

* On-Chip Address and Control Registers.

* 3.3V+0.165V/-0.165V Power Supply.

* I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O

K7B321825M_Samsungsemiconductor.pdf