Description
K7B323625M K7B321825M Document Title 1Mx36 & 2Mx18 Synchronous SRAM 1Mx36 & 2Mx18-Bit Synchronous Burst SRAM Revision History Rev.No.0.0 0.1 0.2 .
The K7B323625M and K7B321825M are 37,748,736-bit Synchronous Static Random Access Memory designed for high performance second level cache of Pentium a.
Features
* Synchronous Operation.
* On-Chip Address Counter.
* Self-Timed Write Cycle.
* On-Chip Address and Control Registers.
* 3.3V+0.165V/-0.165V Power Supply.
* I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O or 2.5V+0.4V/-0.125V for 2.5V I/O
Applications
* G W, B W, LBO, ZZ. Write cycles are internally selftimed and synchronous. Full bus-width write is done by GW, and each byte write is performed by the combination of W Ex and BW when G W is high. And with CS 1 high, ADSP is blocked to control signals. Burst cycle can be initiated with either the add
