HYB3116405BJ-50 Datasheet - Siemens Semiconductor Group

HYB3116405BJ-50 4M x 4-Bit Dynamic RAM 2k & 4k Refresh

DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns) DRAM (access time 50 ns) DRAM (access time 60 ns) DRAM (access time 70 ns).

3.3V 4M x 4-Bit EDO-Dynamic RAM HYB3116405BJ/BT(L) -50/-60/-70 HYB3117405BJ/BT(L) -50/-60/-70 Advanced Information 4 194 304 words by 4-bit organization 0 to 70 °C operating temperature Performance -50 tRAC tCAC tAA tRC tHPC RAS access time CAS access time Access time from address Read/Write cycle time Hyper page mode (EDO) cycle time 50 13 25 84 20 -60 60 15 30 104 25 -70 70 20 35 124 30 ns ns ns ns ns .

HYB3116405BJ-50 Features

* include single + 3.3 V (± 0.3 V) power supply, direct interfacing with high-performance logic device families.The HYB3116405BTL parts have a very low power „sleep mode“ supported by Self Refresh. Ordering Information Type HYB 3117405BJ-50 HYB 3117405BJ-60 HYB 3117405BJ-70 HYB 3117405BT-50 HYB 31174

HYB3116405BJ-50 Datasheet (285.45 KB)