HYB39S16160CT-7 Datasheet - Siemens Semiconductor

HYB39S16160CT-7 1M x 16 MBit Synchronous DRAM

LVTTL-version: HYB 39S16160CT-6 HYB 39S16160CT-7 P-TSOPII-50 (400mil) P-TSOPII-50 (400mil) 166MHz 2B x 512k x 16 SDRAM 143MHz 2B x 512k x 16 SDRAM Pin Description and Pinouts: CLK CKE CS RAS CAS WE A0-A10 A11 (BS) Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write .

www.DataSheet4U.com HYB39S16160CT-6/-7 16MBit Synchronous DRAM 1M x 16 MBit Synchronous DRAM for High Speed Graphics Applications High Performance: -6 fCKmax @ CL=3 tCK3 tAC3 fCKmax @ CL=2 tCK2 tAC2 166 6 5 125 8 6 -7 143 7 5.5 115 9 6 Units MHz ns ns MHz ns ns full page(optional) for sequencial wrap around Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge Data.

HYB39S16160CT-7 Features

* ck, a RAS cycle starts. According to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the word line a

HYB39S16160CT-7 Datasheet (173.11 KB)