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XC9500XL - High-Performance CPLD

Datasheet Summary

Description

Each XC9500XL device is a subsystem consisting of multiple Function Blocks (FBs) and I/O Blocks (IOBs) fully interconnected by the FastCONNECT II switch matrix.

The IOB provides buffering for device inputs and outputs.

Features

  • Optimized for high-performance 3.3V systems - 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz - Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package) - Pb-free available for all packages - Lower power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.35 micron feature size CMOS FastFLASH technology.
  • Advanced system features - In-system programmable - Superior pin-l.

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Datasheet preview – XC9500XL

Datasheet Details

Part number XC9500XL
Manufacturer Xilinx
File Size 214.10 KB
Description High-Performance CPLD
Datasheet download datasheet XC9500XL Datasheet
Additional preview pages of the XC9500XL datasheet.

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Full PDF Text Transcription

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k 0 R XC9500XL High-Performance CPLD Family Data Sheet DS054 (v2.5) May 22, 2009 0 0 Product Specification Features • Optimized for high-performance 3.3V systems - 5 ns pin-to-pin logic delays, with internal system frequency up to 208 MHz - Small footprint packages including VQFPs, TQFPs and CSPs (Chip Scale Package) - Pb-free available for all packages - Lower power operation - 5V tolerant I/O pins accept 5V, 3.3V, and 2.5V signals - 3.3V or 2.5V output capability - Advanced 0.
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